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HTG12N0 4-Bit Microcontroller
Features
* * * * * * * *
Operating voltage: 2.4V~3.5V Seven input lines Six output lines Halt feature reduces power consumption Up to 4s instruction cycle with 1MHz system clock 4K x 8 x 4 program ROM Data memory RAM size 256 x 4 bits 64 segments x 8 commons, 1/5 bias LCD driver
* * * * * * *
8-bit table read instruction Five working registers Internal timer overflow One level subroutine nesting RC oscillator and 32768Hz crystal oscillator 8-bit timer with internal or external clock source Sound effect circuit
General Description
The HTG12N0 is the processor from HOLTEK's 4-bit stand alone single chip microcontroller specially designed for LCD display and time piece product applications. It is ideally suited for multiple LCD time piece low power applications among which are calculators, scales, calendar and hand held LCD products.
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Block Diagram
Notes: ACC: Accumulator PB0, PB1: ROM bank switch PC1: LCD On/Off switch PS, PM0~PM2: Input ports
R0~R4: Working registers PC0: RAM bank switch PA, PC2~PC3: Output ports
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Pad Assignment
Chip size: 3430 x 3730 (m)2 * The IC substrate should be connected to VSS in the PCB layout artwork.
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Pad Coordinates
Pad No.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 Unit: m
X
-1592.40 -1592.40 -1592.40 -1592.40 -1553.16 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1592.40 -1579.60 -1459.36 -1338.80 -1218.56 -1097.52 -965.12 -823.20 -694.08 -552.16 -423.04 -281.12 -152.00
Y
1448.48 1324.64 1207.36 1083.52 508.96 367.52 246.48 125.44 4.40 -116.64 -237.68 -358.72 -479.76 -600.80 -721.84 -842.88 -963.92 -1084.96 -1206.00 -1327.04 -1448.08 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1598.48 -1598.48 -1598.48 -1598.48 -1598.48 -1598.48 -1598.48
Pad No.
34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66
X
-10.08 119.04 290.48 409.20 527.92 646.64 765.36 884.48 1001.44 1117.60 1233.44 1349.60 1465.44 1584.16 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80
Y
-1598.48 -1598.48 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1706.56 -1438.64 -1318.32 -1197.68 -1077.36 -956.72 -836.40 -715.76 -595.44 -474.80 -354.48 -233.84 -113.52 7.12 127.44 248.08 368.40 489.04 609.36 730.00
Pad No.
67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99
X
1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1578.80 1306.40 1185.65 1066.56 947.12 828.00 708.56 589.44 470.00 350.88 231.44 112.32 -7.12 -126.24 -245.68 -364.80 -484.24 -603.36 -722.80 -841.92 -961.36 -1080.48 -1199.92 -1319.04 -1438.48 -1557.60
Y
850.32 970.96 1091.28 1211.92 1332.24 1452.88 1573.20 1695.12 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56 1706.56
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Pad Description
Pad No.
38~99 1~2 3 4 5 6 7 8 29 17 18 9~16 22~25 21~19 26 27, 28 33~30 35~34 36
Pad Name
SEG63~SEG2 SEG1~SEG0 XIN XOUT VDD OSCI OSCO T512 T1D TEST1 TEST2 COM7~COM0 PS3~PS0 PM2~PM0 VSS BZ, BZ PA3~PA0 PC3~PC2 RES
I/O
O I O I I O O O I I O I I O O
Mask Option
-- -- -- --
Description
LCD driver outputs for LCD panel segment 32768Hz crystal oscillator for time base, LCD clock Positive power supply An external resistor between OSCI and OSC0 is needed for the internal system clock. For test mode only TEST1 and TEST2 are left open when the chip is in normal operation (with an internal pull-high resistor).
--
Output for LCD panel common plate
Pull-high or Input pins for input only None, Note 2 -- Note 1 Negative power supply, GND Sound effect outputs
CMOS or NMOS Open Output latch pins for output only Drain -- Input to reset an internal LSI Reset is active on logical low level
I
37
TMCLK
I
Input for TIMER clock Pull-high or TIMER can be clocked by an external clock or an None, Note 3 internal frequency source.
Notes: 1. The system clock provides six different sources selectable by mask option to drive the sound effect clock. If the Holtek sound library is used, only 128K and 64K are acceptable. 2. Each bit of ports PM0~PM2, PS can be a trigger source of the HALT interrupt, selectable by mask option. 3.14 internal clock sources can be selected by mask option to drive TMCLK. Note that TMCLK should not be connected to a pull high resistor if an internal source is used.
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Absolute Maximum Ratings
Supply Voltage ................................. -0.3V~5.5V Input Voltage.....................VSS-0.3V~VDD+0.3V Storage Temperature.................... -50C~125C Operating Temperature..................... 0C~70 C
Note: These are stress ratings only. Stresses exceeding the range specified under "Absolute Maximum Ratings" may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
VDD IDD ISTB1 ISTB2 VIL VIH IOL1 IOH1 IOL2 IOH2 RPH
Ta=25C
Parameter
Operating Voltage Operating Current (LCD ON) Standby Current (LCD OFF) Standby Current (LCD ON) Input Low Voltage Input High Voltage PA, PC, BZ and BZ Output Sink Current PA, PC, BZ and BZ Output Source Current Segment Output Sink Current Segment Output Source Current Pull-high Resistor -- 3V 3V 3V 3V 3V 3V 3V 3V 3V 3V
Test Conditions VDD Conditions
-- No load, fSYS=512kHz HALT mode HALT mode -- -- VOL=0.3V VOH=2.7V VOL=0.3V VOH=2.7V PS, PM, RES, TMCLK
Min.
2.4 -- -- -- 0 0.8VDD 1.5 -0.5 30 -50 15
Typ.
3 100 2 10 -- -- 3 -1 60 -100 100
Max.
3.5 200 5 20 0.2VDD VDD -- -- -- -- 200
Unit
V
A A A
V V mA mA
A A
k
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A.C. Characteristics
Symbol
fSYS fLCD tCOM tCY fTIMER tRES fSOUND Ta=25C
Parameter
System Clock LCD Clock LCD Common Period Cycle Time Timer I/P Frequency (TMCLK) Reset Pulse Width Sound Effect Clock 3V 3V -- 3V 3V -- --
Test Conditions VDD Conditions
R=620k~36k -- 1/8 duty fSYS=1MHz -- -- --
Min.
128 -- -- -- 0 5 --
Typ.
-- 256 (1/fLCD)x8 4 -- -- *64 or 128
Max.
1000 -- -- -- 1000 -- --
Unit
kHz Hz s
s
kHz ms kHz
*: Only these two clocking signal frequencies are supported by Holtek's sound library.
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Functional Description
Program counter - PC
This counter addresses the program ROM and is arranged as a 12-bit binary counter from PC0 to PC11 whose contents specify a maximum of 4096 addresses. The program counter counts with an increment of 1 or 2 with each execution of an instruction. When executing the jump instruction (JMP, JNZ, JC, JTMR,...), a subroutine call, initial reset, internal interrupt, RTC interrupt or returning from a subroutine, the program counter is loaded with the corresponding instruction data as shown in the table. Notes: P0~P11: Instruction code @: PC11 keeps the current value S0~S11: Stack register bits PB0 and PB1 are set to 0 at power on reset.
Program memory - ROM
Program memory PB0=0, PB1=0
The program memory is the executable memory and is arranged in a 4096x8 bit format. There are four banks for the program memory in HTG12N0, each bank shown in the figure can be switched by the assignment of PB0 and PB1. The address is specified by the program counter (PC). Four special locations are reserved as shown below.
Program memory PB0=1, PB1=0
* Location 0
Activating the processor RES pin causes the first instruction to be fetched from location 0.
Mode
Initial reset Internal interrupt External interrupt Jump, call instruction
Program Counter PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PB1 PB1 PB1 PB1 PB0 PB0 PB0 PB0 PB0 PB0 0 0 0 P11 @ S11 0 0 0 P10 P10 S10 0 0 0 P9 P9 S9 0 0 0 P8 P8 S8 0 0 0 P7 P7 S7 0 0 0 P6 P6 S6 0 0 0 P5 P5 S5 0 0 0 P4 P4 S4 0 0 1 P3 P3 S3 0 1 0 P2 P2 S2 0 0 0 P1 P1 S1 0 0 0 P0 P0 S0
Conditional PB1 branch Return from PB1 subroutine
Program memory
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* Location 4
Contains the timer interrupt resulting from a TIMER overflow. If the interrupts are enabled, it causes the program to jump to this subroutine.
* Location 8
Activating the RTC of the processor with the interrupts enabled causes the program to jump to this location.
* Locations n00H to nFFH
Each page in the program memory consists of 256 bytes. This area from n00H to nFFH and F00H to FFFH can be used as a look-up table. Instructions such as READ R4A, READ MR0A, READF R4A, READF MR0A can read the table and transfer the contents of the table to ACC and R4 or to ACC and a data memory address specified by the register pair R1,R0. However as R1,R0 can only store 8 bits, these instructions cannot fully specify the full 12-bit program memory address. For this reason a jump instruction should be used first to place the program counter in the right page. The above instructions can then be used to read the look up table data. Note that the page number n must be greater than zero as some locations in page 0 are reserved for specific usage as mentioned. This area may function as normal program memory as required. The program memory mapping is shown in the diagram. In the execution of an instruction the program counter is added before the execution phase, so careful manipulation of READ MR0A and READ R4A is required in the page margin.
Stack register
Program memory PB0=0, PB1=1
Program memory PB0=1, PB1=1 also cause the PC contents to be pushed onto the stack; however the carry flag will not be stored. At the end of a subroutine or an interrupt routine which is signaled by a return instruction, RET or RETI restore the program counter to its previous value from the stack register. Executing "RETI" instruction will restore the carry flag from the stack register, but "RET" will not.
Working registers - R0, R1, R2, R3, R4
The stack register is a group of registers used to save the contents of the program counter (PC) and is arranged in 13 bits x 1 level. One bit is used to store the carry flag. An interrupt will force the contents of the PC and the carry flag onto the stack register. A subroutine call will
There are five working registers (R0, R1, R2, R3, R4) usually used to store the frequently accessed intermediate results. Using the instructions INC Rn and DEC Rn the working registers can increment (+1) or decrement (-1). The JNZ Rn (n=0,1,4) instruction makes efficient use of the working registers as a program loop counter. Also the register pairs R0,R1 and R2,R3 are used as a data memory pointer when the memory transfer instruction is executed.
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Data memory - RAM
The static data memory (RAM) is arranged in 256x4 bit format and is used to store data. All of the data memory locations are indirectly addressable through the register pair R1,R0 or R3,R2; for example MOV A,[R3R2] or MOV [R3R2],A. There are two banks for data memory in HTG12N0, each bank shown in the figure can be switched by the assignment of PC0. Each bank maps to different area of the data memory. There are two areas in the data memory, the temporary data area and the display data area. Access to the temporary data area is from 00H to 7FH of bank 0 and 00H to 7FH of bank 1, Locations 80H to FFH (don't care the bank pointer) represent the display data area. When data is written into the display data area it is automatically read by the LCD driver which then generates the corresponding LCD driving signals. The relationship between the data pointer RAM locations are shown in the table.
of input to the ALU and the destination of the results of the operations performed in the ALU. Data to and from the I/O ports and memory also passes through the accumulator.
Arithmetic and logic unit - ALU
This circuit performs the following arithmetic and logical operations ...
* * * * * * * *
Add with or without carry Subtract with or without carry AND, OR, Exclusive-OR Rotate right, left through carry BCD decimal adjust for addition Increment, decrement Data transfers Branch decisions
The ALU not only outputs the results of data operations, but also sets the status of the carry flag (CF) in some instructions.
Timer/counter
The HTG12N0 contains a programmable 8-bit count-up counter which can be used to count external events or as a clock to generate an accurate time base. If the 8-bit timer clock is supplied by an external source from pin TMCLK, synchronization problems may occur when reading the data from the timer. It is therefore suggested that the timer is stopped before retrieving the data. The 8-bit counter will increment on the rising edge of the clock whether it is internally or externally generated. The timer/counter may be set and read with software instructions and stopped by a hardware reset or a TIMER OFF instruction. To restart the timer, load the counter with the value XXH and then issue a TIMER ON instruction. Note that XX is the desired start count immediate value of the 8 bits. Once the timer/counter is started it increments to a maximum count of FFH and then overflows to zero (00H). It then continues to count until stopped by a TIMER OFF instruction or a reset. The increment from the maximum count of FFH to zero (00H) triggers a timer flag TF and an internal interrupt request. The interrupt
Data memory
Data memory Display data area (80H~FFH) don't care about the PC0.
Accumulator - ACC
The accumulator is the most important data register in the processor. It is one of the sources
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may be enabled or disabled by executing the EI and DI instructions. If the interrupt is enabled the timer overflow will cause a subroutine call to location 4. The state of the timer flag can also be tested with the conditional jump instruction JTMR. The timer flag is cleared after the interrupt or the JTMR instruction is executed. If an internal source is used, the frequency is determined by the system clock and the parameter n as defined in the equation. The frequency of the internal frequency source can be selected by mask option. Frequency of TIMER clock = system clock 2n where n=0,1,2 ...13 selectable by mask option.
RTC
rupt is activated. This cause a subroutine call to location 4 and resets the timer flag. If both TIMER and RTC interrupts arrive at the same time, the RTC one will be serviced first. When running under a CALL subroutine or DI the interrupt acknowledge is on hold until the RET or EI instruction a invoked. The CALL instruction should not be used within an interrupt routine as unpredictable behaviors may occur. If within a CALL subroutine both TIMER and RTC interrupt occur, no matter what order they arrive in, the RTC interrupt will be serviced first after leaving the CALL subroutine. This also applies if the two interrupt arrive at the same time. The interrupt are disabled by a hardware reset or a DI instruction. They remain disabled until the EI instruction is executed.
Initial reset
There is a real time clock (RTC) function implemented on the HTG12N0. The RTC function is used to generate an accurate time period. The clock source of RTC circuit comes from the 32768Hz crystal oscillator. The block diagram is shown as follows.
The HTG12N0 provides an RES pin for system initialization. This pin is equipped with an internal pull high resistor and in combination with an external 0.1~1F capacitor, it provides an internal reset pulse of sufficient length to guarantee a reset to all internal circuits. If the reset pulse is generated externally, the RES pin must be held low at least 5ms. When RES is active, the internal block will be initialized as shown below: PC 000H Stop Reset (low) Sound off and one sing mode High (or floating state) Disabled
The RTC output can be selected by mask option. Frequency of the RTC output =
256
2n
, n=0~7
TIMER Timer flag, Carry flag SOUND Output port A LCD output
The RTC output is used to generate an interrupt signal.
Interrupt
The HTG12N0 provides both TIMER and RTC interrupt modes. The DI and EI instructions are used to disable and enable the interrupts. When the RTC is activated during enable interrupt mode and the program is not within a CALL subroutine, this causes a subroutine call to location 8 and reset the interrupt latch. Likewise when the timer flag is set in the enable interrupt mode and the program is not within a CALL subroutine, the TIMER inter11
BZ and BZ output High level
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Halt
This is a special feature of the HTG12N0 used to interrupt the chip's normal operation and reduce the power consumption. When a HALT is executed the following happens ...
* The system clock will be stopped * The contents of the on-chip RAM and regis-
Whenever the instruction "SOUND n" or "SOUND A" is executed, the specified sound begins. Each time "SOUND OFF" is executed, it immediately terminates the singing sound. There are two singing modes, SONE mode and SLOOP mode activated by SOUND ONE and SOUND LOOP. In SONE mode the specified sound plays only once. In the SLOOP mode the specified sound keeps re-playing. Since sounds 0~11 contain 32 notes and sounds 12~15 include 64 notes, the latter possesses better sound than the former. The sound effect circuit frequency can be selected by mask option.
ters remain unchanged
* RTC oscillator still keeps running * BZ and BZ keep high level output
The system can quit the HALT mode by way of initial reset or RTC interrupt or wake-up from the following entry of program counter value. Initial reset: 00H Wake-up: next address of the HALT instruction When the halt status is terminated by the RTC interrupt, the following procedure takes place: Case 1: If the system is in an interrupt-disable state before entering the halt state:
* The system will awake and returns to the
Frequencyof sound effect circuit =
...where m=0,1,2,3,4,5.
system clock 2m
Holtek's sound library supports only sound clock frequency of 128K or 64K. To use Holtek's sound library the proper system clock and mask option should be selected.
LCD display memory
main program instruction following the HALT command.
* The RTC interrupt will be held until the sys-
tem receives an enable interrupt command by which the RTC interrupt will be serviced. Case 2: If the system is in an interrupt enable state:
* The RTC interrupt will awake the system and
As mentioned in the data memory section the LCD display memory is embedded in the data memory. It can be read and written to in the same way as normal data memory. The figure illustrates the mapping between the display memory and LCD pattern for the HTG12N0. There is an ON/OFF switch for display controlled by bit 1 of port PC (PC1). The corresponding bit of the PC1 represents "ON" or "OFF" of the LCD display memory. The LCD display module may have any form as long as the number of commons does not exceed 8 and the number of segments is not over 64.
execute the RTC interrupt subroutine. In the HALT mode, each bit of ports PM, PS, can be used as wake-up signal by mask option to wake-up the system. This signal is active in low-going transition.
Sound effects
The HTG12N0 includes sound effect circuitry which offers up to 16 sounds with 3 tones, boom and noise effects. Holtek supports a sound library including melodies, alarms, machine guns etc..
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LCD driver output
All of the LCD segments are random after an initial clear. The bias voltage circuits of the LCD display is built-in and no external resistor is required. The output number of the HTG12N0 LCD driver is 64x8 which can directly drive an LCD with 1/8 duty cycle and 1/5 bias.
An example of an LCD driving waveform (1/8 duty and 1/5 bias) is shown below.
Oscillator
Only one external resistor is required for the HTG12N0 system clock. The system clock is also used as the reference signal of the sound effect clock or internal frequency source of TIMER. Another crystal oscillator is needed for use as the reference signal of LCD driving clock and RTC interrupt clock source. A machine cycle consists of a sequence of four states numbered T1 to T4. Each state lasts for one oscillator period. The machine cycle is 4s if the system frequency is up to 1MHz.
LCD display memory The LCD driving clock frequency is fixed at 256Hz. This is set by the RTC OSC (32.768kHz). LCD driver output can be enabled or disabled by setting PC1 without the influence of the related memory condition. LCD driver output is enabled by setting PC1 as "1", and disabled by setting PC1 as "0".
RC and RTC oscillator
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Interfacing Mask options
The HTG12N0 microcontroller communicates with the outside world through 7-bit input pins PS and PM0~PM2 and 6-bit output pins PA and PC2~PC3.
Input ports - PS, PM0~PM2
HTG12N0 provides seven kinds of mask option for different applications.
* Each bit of input ports PS, PM0~PM2 with
pull-high resistor
* Each bit of input ports PS, PM0~PM2 func-
All of the ports can have internal pull high resistors determined by mask option. Every bit of the input ports PS and PM0~PM2 can be specified to be a trigger source for waking up the HALT interrupt by mask option. A high to low transition on one of these pins will wake up the device from a HALT status.
tion as HALT wake-up trigger
* Each bit of output port PA, PC2~PC3 with
CMOS or open drain NMOS
* 8-bit programmable TIMER with internal or
external frequency sources. There are 14 internal frequency sources which can be selected as a clocking signal. If using internal frequency sources as clocking signal TMCLK cannot connect with a pullhigh resistor.
* Six kinds of sound clock frequencies:
fSYS/2m, m=0, 1, 2, 3, 4, 5
* There are eight kinds of RTC interrupt fre-
quencies. RTC interrupt frequency=256/2n Hz, n=0~7. and 60A for suitable size of LCD panel.
Input ports PS, PM0~PM2
* Three kinds of LCD bias current, 6A, 15A
Output port - PA, PC2~PC3
A mask option is available to select whether the output is of a CMOS or open drain NMOS type. After an initial clear the output port PA and PC2~PC3 defaults to be high for CMOS or floating for NMOS.
Output port PA and PC2~PC3
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Application Circuits
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Instruction Set Summary
Mnemonic
Arithmetic ADD A,[R1R0] ADC A,[R1R0] SUB A,[R1R0] SBC A,[R1R0] ADD A,XH SUB A,XH DAA Logic Operation AND A,[R1R0] OR A,[R1R0] XOR A,[R1R0] AND [R1R0],A OR [R1R0],A XOR [R1R0],A AND A,XH OR A,XH XOR A,XH Increment and Decrement INC A INC Rn INC [R1R0] INC [R3R2] DEC A DEC Rn DEC [R1R0] DEC [R3R2] Data Move MOV A,Rn MOV Rn,A MOV A,[R1R0] MOV A,[R3R2] MOV [R1R0],A MOV [R3R2],A MOV A,XH MOV R1R0,XXH MOV R3R2,XXH MOV R4,XH Move register to ACC, n=0~4 Move ACC to register, n=0~4 Move data memory to ACC Move data memory to ACC Move ACC to data memory Move ACC to data memory Move immediate data to ACC Move immediate data to R1 and R0 Move immediate data to R3 and R2 Move immediate data to R4 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 2 2 2
-- -- -- -- -- -- -- -- -- --
Description
Byte
Cycle
CF
Add data memory to ACC Add data memory with carry to ACC Subtract data memory from ACC Subtract data memory from ACC with borrow Add immediate data to ACC Subtract immediate data from ACC Decimal adjust ACC for addition
1 1 1 1 2 2 1
1 1 1 1 2 2 1

AND data memory to ACC OR data memory to ACC Exclusive-OR data memory to ACC AND ACC to data memory OR ACC to data memory Exclusive-OR ACC to data memory AND immediate data to ACC OR immediate data to ACC Exclusive-OR immediate data to ACC
1 1 1 1 1 1 2 2 2
1 1 1 1 1 1 2 2 2
-- -- -- -- -- -- -- -- --
Increment ACC Increment register, n=0~4 Increment data memory Increment data memory Decrement ACC Decrement register, n=0~4 Decrement data memory Decrement data memory
1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1
-- -- -- -- -- -- -- --
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Mnemonic
Rotate RL A RLC A RR A RRC A Input & Output IN A,Pi OUT Pi,A Branch JMP addr JC addr JNC addr JTMR addr JAn addr JZ A,addr JNZ A,addr JNZ Rn,addr Subroutine CALL addr RET RETI Flag CLC STC EI DI NOP Timer TIMER XXH TIMER ON TIMER OFF MOV A,TMRL MOV A,TMRH MOV TMRL,A MOV TMRH,A Table Read READ R4A READ MR0A READF R4A READF MR0A Read ROM code of current page to R4 and ACC Read ROM code of current page to M(R1,R0), ACC Read ROM code of page F to R4 and ACC Read ROM code of page F to M(R1,R0),ACC 1 1 1 1 2 2 2 2
-- -- -- --
Description
Byte
Cycle
CF
Rotate ACC left Rotate ACC left through the carry Rotate ACC right Rotate ACC right through the carry
1 1 1 1
1 1 1 1

Input port-i to ACC, port-i=PM0~PM2,PS Output ACC to port-i, port-i=PC2~PC3, PA
1 1
1 1
-- --
Jump unconditionally Jump on carry=1 Jump on carry=0 Jump on timer overflow Jump on ACC bit n=1 Jump on ACC is zero Jump on ACC is not zero Jump on register Rn not zero, n=0,1,4
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
-- -- -- -- -- -- -- --
Subroutine call Return from subroutine or interrupt Return from interrupt service routine
2 1 1
2 1 1
-- --
Clear carry flag Set carry flag Enable interrupt Disable interrupt No operation
1 1 1 1 1
1 1 1 1 1
0 1
-- -- --
Set 8 bits immediate data to TIMER Set TIMER start counting Set TIMER stop counting Move low nibble of TIMER to ACC Move high nibble of TIMER to ACC Move ACC to low nibble of TIMER Move ACC to high nibble of TIMER
2 1 1 1 1 1 1
2 1 1 1 1 1 1
-- -- -- -- -- -- --
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Mnemonic
Sound Control SOUND n SOUND A SOUND ONE SOUND LOOP SOUND OFF Miscellaneous HALT Enter power down mode 2 2
--
Description
Byte
Cycle
CF
Activate SOUND channel n Activate SOUND channel with ACC Turn on SOUND one cycle Turn on SOUND repeat cycle Turn off SOUND
2 1 1 1 1
2 1 1 1 1
-- -- -- -- --
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Instruction Definitions
ADC A,[R1R0]
Add data memory contents and carry to accumulator 00001000 The contents of the data memory addressed by the register pair "R1,R0" and the carry are added to the accumulator. Carry is affected. ACC ACC+M(R1,R0)+C Add immediate data to accumulator 01000000 ACC ACC+XH Add data memory contents to accumulator 00001001 The contents of the data memory addressed by the register pair "R1,R0" is added to the accumulator. Carry is affected. ACC ACC+M(R1,R0) Logical AND immediate data to accumulator 01000010 0000dddd Data in the accumulator is logical AND with the immediate data specified by a code. ACC ACC "AND" XH Logical AND accumulator with data memory 00011010 Data in the accumulator is logical AND with the data memory addressed by the register pair "R1,R0". ACC ACC "AND" M(R1,R0) Logical AND data memory with accumulator 00011101 Data in the data memory addressed by the register pair "R1,R0" is logical AND with the accumulator M(R1,R0) M(R1,R0) "AND" ACC 0000dddd The specified data is added to the accumulator. Carry is affected.
Machine Code Description Operation
ADD A,XH
Machine Code Description Operation
ADD A,[R1R0]
Machine Code Description Operation
AND A,XH
Machine Code Description Operation
AND A,[R1R0]
Machine Code Description Operation
AND [R1R0],A
Machine Code Description Operation
19
18th Mar '99
HTG12N0
CALL address
Subroutine call 1111aaaa aaaaaaaa The program counter bits 0~11 are saved in the stack. The program counter is then loaded from the directly-specified address. Stack PC+2 PC address Clear carry flag 00101010 The carry flag is reset to zero. C0 Decimal-Adjust accumulator 00110110 The accumulator value is adjusted to the BCD (Binary Code Decimal) code, if the contents of the accumulator is greater than 9 or C (Carry flag) is one. If ACC>9 or CF=1 then ACC ACC+6, C 1 else ACC ACC, C C Decrement accumulator 00111111 Data in the accumulator is decremented by one. Carry flag is not affected. ACC ACC-1 Decrement register 0001nnn1 Data in the working register "Rn" is decremented by one. Carry flag is not affected. Rn Rn-1; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4 Decrement data memory 00001101 Data in the data memory specified by the register pair "R1,R0" is decremented by one. Carry flag is not affected. M(R1,R0) M(R1,R0)-1
Machine Code Description Operation
CLC
Machine Code Description Operation
DAA
Machine Code Description Operation
DEC A
Machine Code Description Operation
DEC Rn
Machine Code Description Operation
DEC [R1R0]
Machine Code Description Operation
20
18th Mar '99
HTG12N0
DEC [R3R2]
Decrement data memory 00001111 Data in the data memory specified by register pair "R3,R2" is decremented by one. Carry flag is not affected. M(R3,R2) M(R3,R2)-1 Disable interrupt 00101101 Internal time-out interrupt and external interrupt are disabled. Enable interrupt 00101100 Internal time-out interrupt and external interrupt are enabled. Halt system clock 00110111 PC (PC)+1 Input port to accumulator 0 0 1 1 0 0 1 0 PM ACC Pi; Pi=PM or PS Increment accumulator 00110001 Data in the accumulator is incremented by one. Carry flag is not affected. ACC ACC+1 Increment register 0001nnn0 Data in the working register "Rn" is incremented by one. Carry flag is not affected. Rn Rn+1; Rn=R0,R1,R2,R3,R4 for nnn=0,1,2,3,4 Increment data memory 00001100 Data in the data memory specified by the register pair "R1,R0" is incremented by one. Carry flag is not affected. M(R1,R0) M(R1,R0)+1 0 0 1 1 0 0 1 1 PS The data on port "Pi" is transferred to the accumulator. 00111110 Turn off system clock, and enter power down mode.
Machine Code Description Operation
DI
Machine Code Description
EI
Machine Code Description
HALT
Machine Code Description Operation
IN A,Pi
Machine Code Description Operation
INC A
Machine Code Description Operation
INC Rn
Machine Code Description Operation
INC [R1R0]
Machine Code Description Operation
21
18th Mar '99
HTG12N0
INC [R3R2]
Increment data memory 00001110 Data memory specified by the register pair "R3,R2" is incremented by one. Carry flag is not affected. M(R3,R2) M(R3,R2)+1 Jump if accumulator Bit n is set 100nnaaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator bit n is set to one. PC (bit 0-10) address, if ACC bit n=1(n=0,1,2,3,) PC PC+2, if ACC bit n=0 Jump if carry is set 11000aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the C (Carry flag) is set to one. PC (bit 0~10) address, if C=1 PC PC+2, if C=0 Direct Jump 1110aaaa aaaaaaaa Bits 0~11 of the program counter are replaced with the directly-specified address. PC address Jump if carry is not set 11001aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the C (Carry flag) is set to zero. PC (bit 0~10) address, if C=0 PC PC+2, if C=1 Jump if accumulator is not zero 10111aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is not zero. PC (bit 0~10) address, if ACC0 PC PC+2, if ACC=0
Machine Code Description Operation
JAn address
Machine Code Description
Operation
JC address
Machine Code Description
Operation
JMP address
Machine Code Description Operation
JNC address
Machine Code Description
Operation
JNZ A,address
Machine Code Description
Operation
22
18th Mar '99
HTG12N0
JNZ Rn,address
Jump if register is not zero 10100aaa 10101aaa 11011aaa a a a a a a a a R0 a a a a a a a a R1 a a a a a a a a R4
Machine Code
Description
Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the register is not zero. PC (bit 0~10) address, if Rn0; Rn=R0,R1,R4 PC PC+2, if Rn=0 Jump if time-out 11010aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the TF (Timer flag) is set to one. PC (bit 0~10) address, if TF=1 PC PC+2, if TF=0 Jump if accumulator is zero 10110aaa aaaaaaaa Bits 0~10 of the program counter are replaced with the directly-specified address, bit 11 of the program counter and PA3 of the memory bank remain, if the accumulator is zero. PC (bit 0~10) address, if ACC=0 PC PC+2, if ACC0 Move register to accumulator 0010nnn1 Data in the working register "Rn" is moved to the accumulator. ACC Rn; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4 Move timer to accumulator 00111011 The high nibble data of the Timer counter is loaded to the accumulator. ACC TIMER (high nibble) Move timer to accumulator 00111010 The low nibble data of the Timer counter is loaded to the accumulator. ACC TIMER (low nibble)
Operation
JTMR address
Machine Code Description
Operation
JZ A,address
Machine Code Description
Operation
MOV A,Rn
Machine Code Description Operation
MOV A,TMRH
Machine Code Description Operation
MOV A,TMRL
Machine Code Description Operation
23
18th Mar '99
HTG12N0
MOV A,XH
Move immediate data to accumulator 0111dddd The 4-bit data specified by code is loaded to the accumulator. ACC XH Move data memory to accumulator 00000100 Data in the data memory specified by the register pair "R1,R0" is moved to the accumulator. ACC M(R1,R0) Move data memory to accumulator 00000110 Data in the data memory specified by the register pair "R3,R2" is moved to the accumulator. ACC M(R3,R2) Move immediate data to R1 and R0 0101dddd 0000dddd The 8-bit data specified by code are loaded to the working registers R1 and R0, the high nibble of the data is loaded to the R1, and the low nibble of the data is loaded to the R0. R1 XH (high nibble) R0 XH (low nibble) Move immediate data to R3 and R2 0110dddd 0000dddd The 8-bit data specified by code are loaded to the working register R3 and R2, the high nibble of the data is loaded to the R3, and the low nibble of the data is loaded to the R2. R3 XH (high nibble) R2 XH (low nibble) Move immediate data to R4 01000110 R4 XH 0000dddd The 4-bit data specified by code are loaded to the working register R4.
Machine Code Description Operation
MOV A,[R1R0]
Machine Code Description Operation
MOV A,[R3R2]
Machine Code Description Operation
MOV R1R0,XXH
Machine Code Description
Operation
MOV R3R2,XXH
Machine Code Description
Operation
MOV R4,XH
Machine Code Description Operation
24
18th Mar '99
HTG12N0
MOV Rn,A
Move accumulator to register 0010nnn0 Data in the accumulator is moved to the working register "Rn". Rn ACC; Rn=R0,R1,R2,R3,R4, for nnn=0,1,2,3,4 Move accumulator to timer 00111101 The contents of accumulator is loaded to the high nibble of the timer counter. TIMER (high nibble) ACC Move accumulator to timer 00111100 The contents of accumulator is loaded to the low nibble of the timer counter. TIMER (low nibble) ACC Move accumulator to data memory 00000101 Data in the accumulator is moved to the data memory specified by the register pair "R1,R0". M(R1,R0) ACC Move accumulator to data memory 00000111 Data in the accumulator is moved to the data memory specified by the register pair "R3,R2". M(R3,R2) ACC No operation 00111110 Do nothing, but one instruction cycle is delayed. Logical OR immediate data to accumulator 01000100 0000dddd Data in the accumulator is logical OR with the immediate data specified by code. ACC ACC "OR" XH
Machine Code Description Operation
MOV TMRH,A
Machine Code Description Operation
MOV TMRL,A
Machine Code Description Operation
MOV [R1R0],A
Machine Code Description Operation
MOV [R3R2],A
Machine Code Description Operation
NOP
Machine Code Description
OR A,XH
Machine Code Description Operation
25
18th Mar '99
HTG12N0
OR A,[R1R0]
Logical OR accumulator with data memory 00011100 Data in the accumulator is logically OR with the data memory addressed by the register pair "R1,R0". ACC ACC "OR" M(R1,R0) Logical OR data memory with accumulator 00011111 Data in the data memory addressed by the register pair "R1,R0" is logical OR with the accumulator. M(R1,R0) M(R1,R0) "OR" ACC Output accumulator data to port-i 0 0 1 1 0 0 0 0 PA 0 0 1 1 0 1 0 0 PC The data in the accumulator is transferred to the port-i and latched. Pi ACC; Pi=PA or PC Read ROM code of current page to M(R1,R0) and ACC 01001110 The 8-bits of ROM code (current page) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to accumulator. The address of the ROM code are specified below : Current page ROM code address bit 12~8 ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1R0) ROM code (high nibble) ACC ROM code (low nibble) Read ROM code of current page to R4 and accumulator 01001100 The 8-bits of ROM code (current page) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. The address of the ROM code are specified below: Current page ROM code address bit 12~8 ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 ROM code (high nibble) ACC ROM code (low nibble)
Machine Code Description Operation
OR [R1R0],A
Machine Code Description Operation
OUT Pi,A
Machine Code Description Operation
READ MR0A
Machine Code Description
Operation
READ R4A
Machine Code Description
Operation
26
18th Mar '99
HTG12N0
READF MR0A
Read ROM Code of page F to M(R1,R0) and ACC 01001111 The 8-bit ROM code (page F) addressed by ACC and R4 are moved to the data memory M(R1,R0) and accumulator. The high nibble of the ROM code is loaded to M(R1,R0) and the low nibble of the ROM code is loaded to the accumulator. page F ROM code address bit 12~8 are "PA3 1111" ACC ROM code address bit 7~4 R4 ROM code address bit 3~0 M(R1,R0) high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Read ROM code of page F to R4 and accumulator 01001101 The 8-bit ROM code (page F) addressed by ACC and M(R1,R0) are moved to the working register R4 and accumulator. The high nibble of the ROM code is loaded to R4 and the low nibble of the ROM code is loaded to the accumulator. page F ROM code address bit 12~8 are "PA3 1111" ACC ROM code address bit 7~4 M(R1,R0) ROM code address bit 3~0 R4 high nibble of ROM code (page F) ACC low nibble of ROM code (page F) Return from subroutine or interrupt 00101110 The program counter bits 0~11 are restored from the stack. PC Stack Return from interrupt subroutine 00101111 The program counter bits 0~11 are restored from the stack. The carry flag before entering the interrupt service routine is restored. PC Stack C C (before interrupt service routine) Rotate accumulator left 00000001 The contents of the accumulator are rotated left one bit. Bit 3 is rotated to bit 0 and carry flag. An+1 An; An: accumulator bit n (n=0,1,2) A0 A3 C A3
Machine Code Description
Operation
READF R4A
Machine Code Description
Operation
RET
Machine Code Description Operation
RETI
Machine Code Description Operation
RL A
Machine Code Description Operation
27
18th Mar '99
HTG12N0
RLC A
Rotate accumulator left through carry 00000011 The contents of the accumulator are rotated left one bit. Bit 3 replaces the carry bit; the carry bit is rotated into the bit 0 position. An+1 An; An: Accumulator bit n (n=0,1,2) A0 C C A3 Rotate accumulator right 00000000 The contents of the accumulator are rotated right one bit. Bit 0 is rotated to bit 3 and carry flag. An An+1; An: Accumulator bit n (n=0,1,2) A3 A0 C A0 Rotate accumulator right through carry 00000010 The contents of the accumulator are rotated right one bit. Bit 0 replaces the carry bit; the carry bit is rotated into the bit 3 position. An An+1; An: Accumulator bit n (n=0,1,2) A3 C C A0 Subtract data memory contents and carry from ACC 00001010 The contents of the data memory addressed by the register pair "R1,R0" and the carry are subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+CF Active SOUND channel with accumulator 01001011 The activated sound begins playing in accordance with the contents of the accumulator when the specified sound channel is matched. Turn on sound repeat mode 01001001 The activated sound plays repeatedly. Turn off sound 01001010 The singing sound will terminate immediately.
Machine Code Description Operation
RR A
Machine Code Description Operation
RRC A
Machine Code Description Operation
SBC A,[R1R0]
Machine Code Description Operation
SOUND A
Machine Code Description
SOUND LOOP
Machine Code Description
SOUND OFF
Machine Code Description
28
18th Mar '99
HTG12N0
SOUND ONE
Turn on sound one mode 01001000 The activated sound plays only one time. Active SOUND Channel n 0000nnnn 01000101 The specified sound begins playing and overwriting the previous singing sound. (nnn=0~15) Set carry flag 00101011 The carry flag is set to one. C1 Subtract immediate data from accumulator 01000001 ACC ACC+XH+1 Subtract data memory contents from accumulator 00001011 The contents of the data memory addressed by the register pair "R1,R0" is subtracted from the accumulator. Carry is affected. ACC ACC+M(R1,R0)+1 Set timer to stop counting 00111001 The timer stops counting when the "TIMER OFF" instruction is executed. Set timer start counting 00111000 The timer starts counting when the "TIMER ON" instruction is executed. Set immediate data to timer counter 01000111 TIMER XXH dddddddd The 8-bit data specified by code is loaded to the Timer counter. 0000dddd The specified data is subtracted from the accumulator. Carry is affected.
Machine Code Description
SOUND n
Machine Code Description
STC
Machine Code Description Operation
SUB A,XH
Machine Code Description Operation
SUB A,[R1R0]
Machine Code Description Operation
TIMER OFF
Machine Code Description
TIMER ON
Machine Code Description
TIMER XXH
Machine Code Description Operation
29
18th Mar '99
HTG12N0
XOR A,XH
Logical XOR immediate data to accumulator 01000011 0000dddd Data in the accumulator is Exclusive-OR with the immediate data specified by code. ACC ACC "XOR" XH Logical XOR accumulator with data memory 00011011 Data in the accumulator is Exclusive-OR with the data memory addressed by the register pair "R1,R0". ACC ACC "XOR" M(R1,R0) Logical XOR data memory with accumulator 00011110 Data in the data memory addressed by the register pair "R1,R0" is logically Exclusive-OR with the accumulator. M(R1,R0) M(R1,R0) "XOR" ACC
Machine Code Description Operation
XOR A,[R1R0]
Machine Code Description Operation
XOR [R1R0],A
Machine Code Description Operation
30
18th Mar '99

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